As compared with a traditional neutral point clamped (NPC, diode neutral point clamped) inverter, an active neutral point clamped (ANPC) inverter includes a controllable switch to replace a clamping diode, in order to increase the number of degrees of freedom of the control system and achieve many control objectives.
FIG. 1 shows a topology of one bridge leg of an ANPC three-level inverter. The bridge leg includes switches T1 to T6, in which T1, T2 and T5 are respectively an outer transistor, an inner transistor and a clamping transistor of an upper half bridge leg, and T4, T3 and T6 are respectively an outer transistor, an inner transistor and a clamping transistor of a lower half bridge leg. In order to generate three levels (−uDC/2, 0 and uDC/2, where uDC is a direct-current bus voltage), conventional technology utilizes a modulation scheme that operates the two inner transistors at a high frequency while operating the two outer transistors and the two clamping transistors at the grid frequency. For example, FIG. 2 shows waveforms (sans a dead zone) of drive signals of the switches in the modulation scheme, where uO* represents an output voltage instruction of the bridge leg, and M2_gT1 to M2_gT6 represent the waveforms of the drive signals of T1 to T6 in one period of the power frequency respectively.
With this modulation scheme, it can be ensured that a maximum voltage borne by the switches is uDC/2 in both a positive half period and a negative half period of an output voltage of the bridge leg. However, switch states of at least four switches in the bridge leg are required to change simultaneously (referring to a time to) when zero-crossing switching occurs in uO*. It is an ideal case that switching actions of the switches can be completed simultaneously, and the maximum voltage borne by T1 to T6 is still uDC/2. In fact, some of the switching actions of the switches may be completed before others, which results in a risk of overvoltage for some switches.